1. Field of the Invention
This invention relates generally to an electrically alterable non-volatile memory device, such as an EEPROM and a flash memory, and, more specifically, to those types of devices employing split gate structures.
2. Description of the Related Art
Numerous electrically alterable non-volatile semiconductor memory devices such as EEPROMs (electrically erasable programmable read-only-memory) and flash memories have been developed.
Although erasing of EEPROMs is achieved electrically, one problem which occurs during an erase operation of the prior art EEPROM device, is that it cannot be over-erased. If a memory cell of the device is over-erased, it will become a depletion transistor, and it will conduct leakage current during reading of the other memory cells on the same access line. In order to overcome this problem in an ordinary EEPROM device, a memory cell is verified in a chip or in a bit to ensure that the over-erase condition does not occur. However, this necessitates an additional verification circuit and takes a relatively long time for the EEPROM device.
In one approach to overcome the above-mentioned disadvantages, a memory device is fabricated, including a floating gate formed between a control gate electrode and the surface of a semiconductor substrate, both of which are contiguous to a source region and a portion of a channel region and an addressing gate or select gate is formed on the channel region and extending to a portion of the channel region not covered by the floating gate and the control gate electrode. Due to the presence of the addressing gate, this device will not leak current even if the floating gate transistor is over-erased because the addressing gate can still turn off the device. The structure effectively includes a floating gate transistor and an addressing gate transistor in series and is referred to as a split gate structure.
For accomplishing the erasing, the memory cells are provided with a third gate or control gate. The control gate passes through each memory cell transistor closely adjacent to a surface of the floating gate but insulated therefrom by a dielectric layer. Charge is then removed from the floating gate to channel and drain regions of the cell, when appropriate voltages are applied to transistor elements, such as a drain region and control gate.
A plurality of memory cells are generally arranged in a matrix in conventional memory devices. In some instances, erasing can be carried out simultaneously for a significant group of, or the entire array of memory cells, which is referred to as a flash EEPROM memory array.
This is in contrast to prior EEPROMS which have additional gating devices for each cell and which are erased bit by bit. Rapid advancement in high integration has been accomplished primarily by this simultaneous erasing of the significant group of, or predetermined unit of memory cells of the flash EEPROMs. The unit is either a predetermined portion of the integrated device, which are hereinafter referred to as a `block`, or the entire portion of a memory device. The unit tends to be larger in size with the increase in the integration.
Since flash memory devices have been regarded as being used interchangeably with ultra-violet light erasable EPROMs until recently, the unit size during erasing has not been of the primary concern. However, as application fields of the flash memory expands it becomes more desirable for the unit size to be arbitrarily selected.
An example of a flash memory device is disclosed in U.S. Pat. No. 5,280,446, which teaches memory cells with a split-gate structure.
FIG. 1 A is a schematic representation of a memory array described in the disclosure, and this array architecture is formed with a plurality of flash memory cells which have a triple layer polysilicon construction as illustrated in a cross sectional view of FIG. 1B.
In this array architecture, there are formed elongated source and drain diffusion layers 4 and 2 parallel to each other in a silicon substrate. A major surface of the substrate is first oxidized to form a tunnel oxide layer, and a first doped polysilicon layer is deposited thereon and defined to form a floating gate 6. The floating gate 6 is formed such that a portion thereof overlaps the drain diffusion layer 2 and is offset from the source diffusion layer 4 by a predetermined distance. A control gate 8 is further formed over the floating gate 6 and parallel to source and drain diffusion layers 4 and 2, having an underlying insulation layer.
In addition, an elongated select gate layer 10 is formed overlying the control gate 8 and portions of the substrate running perpendicular to source and drain layers 4 and 2, and having another underlying insulation layer. A select channel region is thereby defined as a portion of the channel region beneath the select gate 10 between the edge of the floating gate 6 and the source layer 4.
In the memory array architecture of FIG. 1A, the source and drain diffusion layers 4 and 2 are each formed by an elongated diffusion layer in common to a plurality of memory cells. Furthermore, since the drain diffusion layers 2 in this example are formed in common to each pair of neighboring memory cells, this amounts to 2028 drain diffusion layers formed in common, while 1028 source diffusion layers 4 are formed in common to memory cells of one side of the neighboring cells.
In addition, the drain diffusion layer 2 is connected to a metal virtual ground (VG) line 12 via a contact hole, and the source diffusion layer 4 is connected to a metal bit line 14 via another contact hole.
Since a plurality of the control gates 8 are formed extending parallel to the direction of the diffusion layers 4 and 2 and being in common to the both side of the drain diffusion layer 2, this amounts to 2028 control gates formed in common and connected to one another.
A plurality of the select gates 10 are formed extending perpendicular to the direction of the diffusion layers 2 and 4, and are interconnected to form a plurality of word lines (WL).
In the memory array of FIG. 1, a plurality of the select gates 10 are formed extending perpendicular to the control gate 8 so that the source and drain diffusion layers 4 and 2 of a plurality of memory cells can be formed in common as mentioned-above, and the number of contacts between the diffusion layers 2, 4 and the metal lines 12, 14 may be reduced, to thereby accomplish the increase in the integration density of the memory device.
In the memory device in the above example, erasing is carried out by applying a negative voltage to the control gate 8 and a positive voltage to the drain diffusion layer 2.
The unit of, or the size of the memory array for which erase operations are carried out has been determined generally by the manner in which control gates are shared in the memory array. That is, a plurality of memory cells which share one single control line are erased simultaneously. For example, 2048 memory cells are simultaneously erased in the above-mentioned memory array.
The size of the unit during erasing in a prior art memory array has neither been selected arbitrarily, nor had enough flexibility for the selection.